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A sequential-access three-microsecond core memory, 1956 March 08

 File — Multiple Containers
Identifier: 16

Scope and Contents

Division 6 Memo M-4218. A proposed core memory is described that has sequential access to 256 registers (word storage locations), can read out a new word every 3 microsecond and has word length of 58 bits. A read-rewrite cycle for a given storage location requires 6 microseconds; the rewrite (or write), is accomplished during the 3 microsecond period that the next storage location is being read. Direct storage location selection provides a 3-to-1 selection ratio. Small, low-coercive-force cores are used (0.047 in. O.D., F398, DCL-5-19S-1). Since currents required are small, transistors can be used instead of tubes. Includes: introduction, principle of operation, register selection switch, and figures.

Dates

  • 1956 March 08

Creator

Access note

This collection is open.

Extent

From the Collection: 3.9 Gigabytes ( 4035 MB in 1835 digital files in 31 folders.)

From the Collection: 56.3 Cubic Feet (in 189 boxes including 142 microfilm reels and 4035 MB in 1835 digital files in 31 folders.)

Language of Materials

From the Series: English

Creator

Repository Details

Part of the Massachusetts Institute of Technology. Libraries. Department of Distinctive Collections Repository

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