A sequential-access three-microsecond core memory, 1956 March 8

Division 6 Memo M-4218. A proposed core memory is described that has sequential access to 256 registers (word storage locations), can read out a new word every 3 microsecond and has word length of 58 bits. A read-rewrite cycle for a given storage location requires 6 microseconds; the rewrite (or write), is accomplished during the 3 microsecond period that the next storage location is being read. Direct storage location selection provides a 3-to-1 selection ratio. Small, low-coercive-force cores are used (0.047 in. O.D., F398, DCL-5-19S-1). Since currents required are small, transistors can be used instead of tubes. Includes: introduction, principle of operation, register selection switch, and figures.